A program for simulation of
semiconductor wafer fabrication
M.G.C.
Resende
Operations Research Center, U. of
California at Berkeley, report number 86-14, 1986.
ABSTRACT
A program for discrete event simulation of a semiconductor wafer fab is
presented, Thc program is designed to serve as a tool in the
investigation of efficient fab shop floor scheduling disciplines. but
can also be used to analyze issues such as fab layout design. capacity
analysis, production forecasts, and fab start-up strategies. The
semiconductor fab scheduling problem is presented and the job shop
model used to represent the problem described. The C implementationof
the model is discussed. Input and output of the model are described by
presenting several test simulations. Future extensions to the model and
research directions are proposed.
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