Ph.D. Thesis

Shop Floor Scheduling of Semiconductor Wafer Manufacturing

by Mauricio G. C. Resende

Department of Industrial Engineering and Operations Research, University of California, Berkeley, 1987

Advisor: C. Roger Glassey

Full thesis [PDF]

Title page, abstract, dedication, acknowledgement, table of contents  [PDF | DjVu]
Chapter 1:  Introduction [PDF | DjVu]
Chapter 2:  Integrated circuit fabrication [PDF | DjVu]
Chapter 3:  Literature review [PDF | DjVu]
Chapter 4:  Network queueing model and simulator [PDF | DjVu]
Chapter 5:  Job release by Starvation Avoidance [PDF | DjVu]
Chapter 6:  Simulation Experiments [PDF | DjVu (part1) | DjVu (part2)]
Chapter 7:  Concluding remarks [PDF | DjVu]
References [PDF | DjVu]

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